1. Field of the Invention
The present invention relates to a signal reproducing circuit in a magnetic recording and reproducing apparatus. More particularly, this invention is concerned with a technique for swiftly recovering the signal reproducing circuit from a transient phenomenon, which derives from an inter-terminal voltage of a reproducing head using an element utilizing a magneto-resistive effect (hereinafter referred to as an MR head) and occurs when an idle state is switched to a read state or MR heads are switched in the read state, in the course of reproducing data from a magnetic recording medium using the MR head.
2. Description of the Related Art
In recent years, the operating speed and storage capacity of a magnetic recording and reproducing apparatus such as a magnetic disk unit has become higher and larger. To permit higher recording density, accordingly, an MR head is being used exclusively for reproduction of data instead of an ordinary inductive thin film magnetic head. This is attributable to the fact that when the MR head is used to reproduce data, since a signal magnetic field independent of the relative speed of a magnetic recording medium in relation to the MR head can be detected, the recording density can be raised by lowering the running speed of the magnetic recording medium. However, the MR head suffers from an unpreferable transient phenomenon deriving from an inter-terminal voltage of the MR head and occurring when an idle state is switched to a read state or heads are switched in the read state. There is therefore an increasing demand for a technique of resolving the transient phenomenon.
FIG. 1 shows the circuitry of a signal reproducing circuit for an MR head in accordance with a prior art, and FIG. 2 shows waveforms indicating operation timing.
In FIG. 1, one terminal of an MR head 1 is connected to a connection line 90 and high-potential power line V1 (for example, 5 V) via a resistor 22, and also connected to the base of an npn transistor I constituting a reproduction amplifier (read amplifier) on the first stage. The other terminal of the MR head 1 is connected to a low-potential power line V2 (for example, 0 V) via a resistor 3 and constant current source 4, and also connected to the base of an npn transistor 8 constituting the read amplifier on the first stage. The collector of the transistor 7 is connected to an output terminal RX and to the power line V1 via a resistor 5. The collector of the transistor 8 is connected to an output terminal RY and to the power line V1 via a resistor 6. Moreover, the emitter of the transistor 7 is connected to one terminal CX of a capacitor 9 and to the power line V2 via a constant current source 10. The emitter of the transistor 8 is connected to the other terminal CY of the capacitor 9 and to the power line V2 via a constant current source 11. The output terminals RX and RY are connected to a demodulation system (not shown).
Moreover, there are shown a Chip Enable signal CE, Read/Write control signal RW, and an AND gate 12 responsive to the Chip Enable signal CE and Read/Write control signal R/W. The constant current source 4 is turned on or off in response to the Chip Enable signal CE. The constant current sources 10 and 11 are turned on or of f in response to an output of the AND gate 12. When the Chip Enable signal CE is low, a magnetic recording and reproducing apparatus including this circuit is brought to an idle state. When the Chip Enable signal CE is high, the magnetic recording and reproducing apparatus is brought to a read or writing state. When the Read/Write control signal R/W is high, a read state is selected. When the Read/Write control signal is low, a writing state is selected.
In this circuitry, when the Chip Enable signal CE is low, that is, the magnetic recording and reproducing apparatus is in the idle state, the constant current sources 4, 10, and 11 are all off. When the Chip Enable signal CE is high, the constant current source 4 is turned on to supply a constant current Is. When the Chip Enable signal CE is high and the Read/Write control signal R/W is high, that is when the magnetic recording and reproducing apparatus is in the read state, the constant current sources 10 and 11 are turned on to supply a constant current Ia.
A current supplied over the power line V1 in the read state flows into the power line V2 by way of the connection line 90, resistor 2, MR head 1, resistor 3, and constant current source 4; flows into the power line V2 by way of the resistor 5, transistor 7, and constant current source 10; and flows into the power line V2 by way of the resistor 6, transistor 8, and constant current source 11.
When the constant current Is (serving as a sense current used to detect a magnetic field in a magnetic recording medium) flows through the MR head 1, a potential difference develops at the terminals of the MR head 1 due to an internal resistance of the MR head. This causes an offset voltage to develop between the bases of the transistors 7 and 8. A current flowing into the transistor 7 therefore becomes larger than a current flowing into the transistor 8. A potential difference equivalent to the offset voltage develops between the output terminals RX and RY.
The capacitor 9 accumulates or releases a charge so as to cancel the potential difference, that is, the offset voltage. The inter-terminal voltage VC of the capacitor 9 balances the emitter voltages of the transistors 7 and 8. The constant current Ia supplied from the constant current sources 10 and 11 therefore flows into the transistors 7 and 8.
Consequently, a signal (output signal VR) whose voltage alternates with a change in internal resistance of the MR head 1 due to a change in magnetic field, that is, a signal whose amplitude changes with the change in magnetic field is output to the output terminals RX and RY. Ideally, an unwanted offset voltage is not sent out.
As mentioned above, in the read state, a bias magnetic field must be applied to the MR head 1 in order to cause the sense current Is to flow. An offset voltage therefore develops at the terminals of the MR head 1. For preventing amplification of the offset voltage, the constant current sources 10 and 11 are used to pass the current Ia into the read amplifier (transistors 7 and 8) on the first stage. This causes a potential difference V0 equivalent to the offset voltage to develop between the terminals CX and CY of the capacitor 9 (See FIG. 2). In short, the offset voltage developing at the terminals of the MR head 1 is canceled with the operation of the capacitor 9. As a result, the output voltage VR developing between the output terminals RX and RY becomes 0 (in other words, the offset voltage is 0). No problem occurs.
By contrast, in the idle state, the sense current Is must be cut off to prevent deterioration of the MR element. As this time, no offset voltage develops at the terminals of the MR head 1. The inter-terminal voltage VC of the capacitor 9 is therefore 0. The output signal VR developing between the output terminals RX and RY is therefore 0 (that is, the offset voltage is 0). No problem occurs.
However, a problem occurs during a transient period during which the idle state is switched to the read state. Specifically, during the transient period, a quick or ideally instantaneous transition must be made from a state in which the inter-terminal voltage VC of the capacitor 9 is 0 (a state in which no charge is accumulated in the capacitor 9) to a state in which the inter-terminal voltage VC equals to a potential difference V0 (a state in which a charge proportional to a potential difference equivalent to the offset voltage is accumulated in the capacitor 9). However, since the capacitor 9 has a considerable time constant, it is unfeasible to realize such an ideal state transition. The offset voltage relative to the MR head 1 cannot therefore be canceled completely by means of the capacitor 9 during the transient period. A transient influence (a spike shown in FIG. 2) proportional to the offset voltage appears in the output signal VR. The transient hinders reproduction of a signal. The transient period should therefore be as short as possible.
Moreover, in the case of a signal reproducing circuit having a plurality of MR heads, when MR heads are switched in the read state, a problem similar to the above one occurs. Specifically, the internal resistances of the MR heads are not always the same but are usually different from one another because of errors occurring during a manufacturing process. Under the circumstances, when MR heads are switched in the read state, a fluctuation in inter-terminal voltage VC of the capacitor 9 occurs during the transient period during which the heads are switched. This is attributable to a difference in inter-terminal voltage between the MR heads deriving from a difference in internal resistances between the MR heads. As a result, a transient influence (a spike in FIG. 2) proportional to the fluctuation in inter-terminal voltage VC appears in the output signal VR.
As mentioned above, the signal reproducing circuit for an MR head in accordance with the prior art has a problem in that, since an unwanted offset voltage is superposed on a reproduced signal during the transient period during which the idle state is switched to the read state or heads are switched in the read state, demodulation cannot be carried out accurately.
Moreover, during the transient period during which the offset voltage develops, data cannot be read from a magnetic recording medium. A gap (an area carrying no data) whose length is proportional to the transient period is formed between data blocks. The storage capacity of a magnetic disk unit must therefore be reduced by an amount of data that can otherwise be stored. This results in a loss in data-handling capacity.